By Bramhananda Marathe,Sandhya Nerale
The goal of this e-book is to supply perception and instinct into the analog and analog-mixed sign method verification. it's also a trip the writer of this publication has been via in an effort to take on sensible layout and verification demanding situations with kingdom of paintings analog and combined sign designs.
Motivation for authoring this book
The electronic layout verification ability set is especially varied than analog layout and verification. generally, the analog block point verification is played via the analog designers, and electronic layout verification is played by way of electronic layout verification engineer. loss of go area ability set makes it tough to accomplish verification at mixed-signal point. as a result, both analog fashion designer engineer should still study complicated electronic verification concepts or electronic layout verification engineer embody analog verification to turn into analog-mixed sign verification engineer. This booklet is written conserving this new development in brain, consequently it covers electronic layout basics, electronic layout verification in addition to analog layout basics, and analog functionality verification.
Organization of this book
Keeping the readers of analog verification or electronic layout verification history in brain, the booklet has first five chapters excited by the basics of the analog layout, electronic layout, and its verification. bankruptcy 6 and bankruptcy 7 specializes in the analog-mixed sign layout verification and behavioral modeling respectively. bankruptcy eight is devoted to the low strength verification options.
Chapter 1: creation to Analog combined sign Verification
This bankruptcy discusses concerning the evolution of the verification methodologies, historical past of analog-mixed sign designs, functions, and destiny tendencies.
Chapter 2: Analog layout basics
The goal of this bankruptcy is to offer an outline of the analog layout basics for electronic layout historical past engineers. significant concentration is given on analog habit, layout standards and their notion instead of layout themselves, akin to voltage/current reference, a number of the simple key analog layout homes equivalent to achieve, band width, fundamentals of jitter, eye diagram, and so forth.
Chapter three: electronic layout basics
In this bankruptcy, we clarify electronic layout circulate, combinational and sequential common sense layout basics, layout for testability, ideas of timing, and timing verification.
Chapter four: Analog Verification
This bankruptcy makes a speciality of analog functionality verification and practical verification lower than the context of combined sign layout hierarchical verification instead of the aspect functionality research of the designs themselves.
Chapter five: electronic layout Verification
This bankruptcy explains the instruments and methodologies which are developed over the interval which are predicated on predictable caliber and verification potency. The bankruptcy comprises the sections at the insurance pushed verification (CDV) technique, statement established verification (ABV) method, and evaluation of the CDV utilizing Open Verification method (OVM).
Chapter 6: Analog-Mixed sign Verification
This bankruptcy discusses concerning the AMS verification levels, selecting the right abstraction of DUT for a given verification problem, AMS verification making plans, testplanning for AMS layout verification, and testbench improvement with re-use in brain.
Chapter 7: Analog Behavioral Modeling
This bankruptcy explains concerning the purposes of analog behavioral versions, modeling method, basic examples of varied analog behavioral modeling kinds, choice of accuracy point of the types according to the verification plan, version verification, and signoff.
Chapter eight: Low strength Verification
The goal of this bankruptcy is to provide an explanation for the low energy layout verification demanding situations, key low strength layout parts, low strength layout innovations, low energy layout and verification cycle, testplanning for low strength layout verification, energy acutely aware electronic, and AMS simulations
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Extra resources for Analog-Mixed Signal Verification
Analog-Mixed Signal Verification by Bramhananda Marathe,Sandhya Nerale